Diffused or implanted resistors on a semiconductor substrate such as silicon may be sensitive to mechanical stress due to piezoresistivity phenomena. So, an increased stress into an integrated circuit (IC) may lead to an increased variation of electrical parameters and a functional failure can happen. For example, the difference between thermal coefficients of silicon and package materials may be a source of internal stress by causing geometric deformations. Also, the packaging process and the package of an IC may be source of stress on the IC.
U.S. Pat. No. 7,437,260 discloses using a particular layout of semiconductor resistors made up with a series of a P-doped resistor and an N-doped resistor, each in an L-shape, and with a very precise selected fixed ratio may theoretically eliminate planar stress dependence at a given temperature. In general, this selected fixed scaling ratio depends on temperature and doping concentration. However, due to variability in the semiconductor manufacturing process, there may be a resistor mismatch, and the ratio cannot be very precise and must be modified with the temperature. In fact, the N-doping and P-doping process are two different and sequential operations that are affected by variability and so a very precise scaling ratio cannot be achieved.
Thus, due to manufacturing process variability and temperature variations during IC's operating time, it may be particularly desirable to obtain an increased control of the scaling factor/ratio to reduce/eliminate the planar stresses sensitivity.